1. Field of the Invention
The present invention relates to an integrated circuit (IC) manufactured by the master slice method, more particularly to a gate array large scale integrated circuit (LSI) manufactured by the master slice method, wherein the desired LSI functions are realized by interconnecting previously prepared circuit elements in accordance with the request of users during the manufacture of the semiconductor.
2. Description of the Prior Art
In gate array LSI's manufactured by the master slice method, it is possible to produce many kinds of IC's of various desirable functions from a single kind of bulk just by changing the wiring layers. Below, a prior art LSI will be described with reference to FIGS. 1 to 3 in the BRIEF DESCRIPTION OF THE DRAWINGS.
FIG. 1 shows a schematic diagram of a prior art gate array LSI for explaining the layout thereof. FIG. 2 shows an enlarged view of the corner portion thereof. The above-mentioned gate array LSI usually comprises an array of unit-cells 1 having transistors, resistors, and other circuit elements and automatically interconnecting domains (channel domains) 21 for connecting the unit-cells 1. At the periphery of the unit-cell array, which comprises most of the logic circuits, input and output (I/O) cell domains 4 are arranged. I/O buffers 3 are located in the I/O cell domain 4 in order to electrically interface with external circuits. The unit-cells 1 are supplied with power through feeder lines 61, 62, and 63. The feeder line 61 is part of a multilayer print and is located at the periphery of the LSI. The feeder lines 62 and 63 branch out from the feeder line 61. In FIG. 1, illustration of the feeder line group, namely the feeder lines 61, 62, and 63, has been omitted to simplify the drawing. Reference numerals 5 and 64 indicate pads and pads for the power source, respectively. Bulks having the above-mentioned constitution are produced in advance in the gate array LSI. In response to the request of users, the interconnections are arranged by computer aided design (CAD) and the like. This allows many kinds of IC's to be supplied to users quickly by just changing the wiring layers.
The recent trend toward greater integration in the above-mentioned gate array LSI's, however, has created a need for increasingly larger channel domain areas 21 and numbers of wiring channels. Two methods to increase the channel domain areas are to increase the LSI area itself and to reduce the size of the element patterns in the chip. However, both methods result in high IC costs. Another method which is easier, is to leave the chip size as it is, but to uniformly reduce the width of the constant width feeder lines (62 and 61 in FIG. 3), thereby increasing the area of the channel domain 21 next to the feeder lines. However, this method also increases the resistance of the feeder lines 62 and 61, thereby increasing the voltage drop at the middle of the feeder lines 62 and 61 and preventing the supply of sufficient electric power to the unit-cells located at the middle portion of the LSI.